Variability-Driven Considerations in the Design of Integrated-Circuit Global Interconnects

Chemical-mechanical planarization (CMP) is an enabling technique to achieve uniformity of dielectric and conductor height in BEOL manufacturing processes. Dummy fill insertion improves the uniformity of metal feature density and enhances the planarization that can be obtained by CMP, but can also change the coupling and total capacitance of interconnects [1], [2]. Additionally, dishing and erosion phenomena change interconnect crosssections [3], and hence affect interconnect capacitance and resistance. The first contribution of this paper is a study of interconnect parasitic variations due to (i) different fill patterns that are nominally “equivalent” with respect to foundry rules, and (ii) dishing and erosion of conductors and dielectric similar to those predicted by ITRS [4]. We show that the fill pattern-dependent variation of coupling capacitance between adjacent wires can exceed 20X; variation of total interconnect capacitance can reach 12%. Dishing and erosion lead to interconnect resistance variations of up to 100%, but have limited impact on interconnect capacitance. The second contribution of this paper is an evaluation of how CMP effects (fill insertion, dishing and erosion) impact the achievable bandwidth and delay of buffered global on-chip interconnects. We show that even in a regime of best-possible fill pattern solutions, CMP-aware design may improve bandwidth by up to 3% and reduce delay by up to 3%; improvements in today’s context of suboptimal fill pattern solutions may well be higher. We also compare the effects of CMP-induced variation and random device variation on design performance, in order to assess the relative significance of CMP-related effects. The remainder of this paper is organized as follows. Section II presents our study of interconnect capacitance variations due to choices among nominally “equivalent” fill patterns. Section III describes RC variations due to dishing and erosion. Section IV compares optimized buffered global interconnect designs based on CMP-aware and CMP-unaware RC modeling. We give conclusions and future directions for research in Section V.